High speed wideband sample-and-hold amplifiers (SHA) are widely used in analog-to-digital data converters (ADC). For a number of reasons including speed limitations of process technology, power consumption and other cost related concerns, it is desirable to increase the bandwidth of a SHA to improve its performance and the performance of an ADC into which it is incorporated for use at higher data rates. This is especially true for circuitry fabricated using standard CMOS process technology, which is the preferred technology for system integration but has inferior circuit speed, compared to other more expensive technologies, such as bipolar, SiGe or III-V semiconductors.
Moreover, when implementing SHAs onto silicon substrates and into packages (e.g., within integrated circuits), there is oftentimes difficulty in interfacing between circuitry within an integrated circuit and bond wires, traces, and/or pads to which this circuitry communicatively couples. This interface is generally referred to as the interface between a silicon chip and a package and/or circuit board. It is often difficult to impedance match at these interfaces. To implement this interfacing, stripline and microstrip transmission lines may be employed.
Stripline and microstrip transmission lines are transverse electromagnetic (TEM) and quasi-TEM structures, respectively. Ideally, waves that propagate on these structures have propagation constants that are predominantly linear with frequency and hence phase velocities that are nearly constant with frequency. In isolation, these lines exhibit a single-ended characteristic impedance, phase velocity and attenuation. For instance, if a transmission line having a 50  characteristic impedance is terminated with a 50  load, there is no reflection at the interface between the transmission line and the load.
However, in actual applications, various non-linearities cause there to be an impedance mismatch at the interface between the silicon chip and package and/or circuit board, which may cause significant signal reflection at the interface and thus degrade signal integrity. Such non-linearities can result from various phenomena.
A first example of such a non-linearity relates to the physical placement of transmission lines. As a pair of striplines or microstrip transmission lines are moved closer to one another, for example, at a package substrate, coupling occurs between those transmission lines that significantly alters the transmission parameters of these lines.
A second example of such a non-linearity relates to the bonding wires themselves. Bonding wires connecting package to silicon die usually exhibit inductive impedance at a multi GHz. data rate. Thus, the bonding wire itself causes an impedance mis-match.
A third example relates to loading. Capacitive loading to a signal path from a bonding pad and/or an electrostatic discharge device (ESD) structure at the silicon die becomes more and more significant as the data rate increases, even if termination resistors are placed very close to the input pads. Furthermore, capacitive loading from transistors at an input of a data amplifier creates short circuits in parallel with the termination resistor and reduces the overall impedance at higher frequencies, which results in reduced bandwidth of the input data amplifier and increased signal reflection at its input.
FIG. 1 (Prior Art) is a schematic diagram illustrating impedance mismatch 100 at an interface of silicon 102 and package/board 104. In a single-ended configuration represented by lumped elements, the mismatch 100 at the interface of silicon and package/board can be represented as shown. At the interface, looking towards the package and/or circuit board side (represented by arrow 106), the impedance is predominantly inductive. In contrast, looking towards the silicon side (represented by arrow 108), the impedance is predominantly capacitive.
FIG. 2 (Prior Art) is a schematic diagram showing a conventional connection of input pads 202, 204 and termination load resistors 206, 208 with a sample and hold amplifier 210, 212 of an ADC (not shown). Each SHA includes an input buffer 214 and an output buffer 216. Particular to SHA in ADC, it is crucial for the circuit to preserve the integrity of data input at pads 202, 204. Distortion of a signal due to bandwidth limitation and reflection caused by input impedance mismatch will degrade data converter performance no matter how accurate are stages following the SHA. A conventional connection of input pads 202, 204 and termination load resistors 206, 208 with the input sample-and-hold amplifier of an ADC may cause such problems.
Bandwidth and impedance mismatch can be reduced by limiting the impact of load capacitance. In commonly-assigned U.S. patent application Ser. No. 10/028,806, now U.S. Pat. No. 6,624,699 B2, entitled “Current-controlled CMOS wideband data amplifier circuits,” by Guangming Yin and Jun Cao, a pair of series inductors is connected to gates of an input differential pair to form a current-controlled CMOS wideband data amplifier circuit having expanded bandwidth. In commonly-assigned U.S. patent application Ser. No. 11/320,402 (US Patent Publication 2007/0024369), entitled “Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection,” by Jun Cao, an inductive network is connected to the wideband data amplifier to improve performance of a conventional differential pair. These solutions represent efforts to improve performance of circuits working in the continuous time domain.